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Architecture of Parallel Processing in Computer Organization
Current Issue
Volume 1, 2014
Issue 2 (May)
Pages: 12-17   |   Vol. 1, No. 2, May 2014   |   Follow on         
Paper in PDF Downloads: 35   Since Aug. 28, 2015 Views: 1790   Since Aug. 28, 2015
Authors
[1]
Prabhudev S Irabashetti, Department of Computer, University of Pune, Maharashtra, India.
[2]
Gawali Anjali B., Vishwabharati Academy’s college of Engg, University of Pune, Maharashtra, India.
[3]
Betkar Akshay S., Vishwabharati Academy’s college of Engg, University of Pune, Maharashtra, India.
Abstract
This paper review the reporting of parallel processing in processor organization. A parallel processing becomes more trendy, the oblige for improvement in parallel processing in processor organization becomes even more significant. Here we evaluate each multiple processor organization, 1) SISD: single instruction single data, 2) SIMD: Single instruction multiple data 3) MISD: Multiple instruction single data and 4) MIMD: Multiple instruction multiple data along with Vector Processor/Array Processor, Symmetric Multiprocessing, NUMA and Cluster.
Keywords
Data, Instruction, IS: Instruction Set, CU: Control Unit, MU: Memory Unit PU: Processing Unit, LM: Local Memory, PE: Processing Element, SMP: Symmetric Multiprocessor, NUMA: Non-Uniform Memory Access
Reference
[1]
Introduction to Parallel Processing, Cornell Theory Center Workshop, 1997.
[2]
O. Serlin, The Serlin Report On Parallel Processing, No.54, pp. 8-13, November 1991.
[3]
Advances in Parallel Computing from the Past to the Future, Dr.P Sammulal, Volume 1, Issue 4, September 2013
[4]
http://www.cse.unsw.edu.au/~cs4211/04s1/seminars/rompo.pdf
[5]
http://groups.engin.umd.umich.edu/vi/w3_workshops/VI_winter04_ganesan.pdf
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